ISP Design Engineer: Senior staff engineer / Staff engineer / Senior engineer

Job responsibilities:

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team

Qualifications:

• 7+ years experience with Digital Design and verification
• Experience / knowledge in Camera Image Signal Processing
• Experience / knowledge in C/C++ programming
• Experience as a Technical Leader to develop Digital System on silicon
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Result oriented and embrace change behaviors
• Experience / knowledge in High Level Synthesis is a plus
• Experience / knowledge in CMOS Image Sensor is a plus
• Language skill: Japanese Business and English Business
• Project management / people management experience / skill is a plus